The present invention relates to a data processing unit with a coprocessor interface. A coprocessor is used in a data processing system to perform special tasks, such as floating point operations, digital signal processing, etc. Many data processors are capable of working in combination with a coprocessor. Usually, a main processor addresses a coprocessor through the system bus. If the main processor decodes a coprocessor instruction, it transfers, for example by means of an exception routine, the coprocessor instruction and respective data to a coprocessor which performs the instruction and transfers back a result to the main processor. During execution of the coprocessor, the main processor usually is set in a wait state.
U.S. Pat. No. 5,603,047 describes such a system. FIG. 7 of U.S. Pat. No. 5,603,047 shows a block diagram of such a coprocessor having 24 registers. A coprocessor instruction has a specific format which is detected during the decode stage of the pipeline shown in FIG. 2 of U.S. Pat. No. 5,603,047. The respective coprocessor instructions are described in column 20 of the U.S. Pat. No. 5,603,047. They include instructions for loading and storing data and control from or to the coprocessor. The coprocessor can be able to perform a variety of functions which might be selected by various programs which can be selected through respective addresses which are transferred to the coprocessor. The coprocessor executes these programs and when finished, the respective results can be transferred to the main processor through respective transfer instructions.
In many applications high speed processing of data is necessary. Therefore, there exist a high demand of performing certain tasks within a single cycle of the system clock. Most instructions of known microprocessors or microcontrollers can be executed within a single cycle due to superscalar and superpipeline techniques. Nevertheless, many special instructions are either not available on, for example, reduced instruction set computers, or need a plurality of execution cycles. Even with the addition of coprocessors these tasks cannot be executed in the requested time due to cumbersome transfer protocols between the main processor and a coprocessor.
Therefore, it is an object of the present invention to provide a data processing unit with a coprocessor interface to overcome the above mentioned problems.
This object is achieved according to the present invention by an apparatus that comprises a data processing unit and at least one coprocessor. The data processing unit comprises a register file having registers, a memory, a plurality of execution units, a coprocessor interface for coupling the at least one coprocessor with the data processing unit, and a pipeline configuration for processing instructions having a fetch stage for fetching an instruction from the memory, a decode stage for decoding an operational code from the instruction, an execution stage for activating one of the execution units, and a write-back stage for writing back from the execution unit. The data processing unit comprises read- and write-lines coupling the register file with the coprocessor for exchanging operands, at least one control line indicating that the coprocessor is busy, and a plurality of control lines from the decode stage for controlling the coprocessor which are operated upon detection of a coprocessor instruction. The coprocessor is using the registers from the register file during execution of the coprocessor instruction. The coprocessor comprises a decode unit for decoding the coprocessor instruction and a plurality of coprocessor execution units that share the decode unit, the decode unit selects one of the coprocessor execution units upon the coprocessor instruction, and the selected one of the coprocessor execution units performs the coprocessor instruction.
Because the coprocessor is using the register file of the main processor it can execute instructions as fast as any execution unit, such as the arithmetic logic unit, a shifter, a load/store unit, etc. A coprocessor instruction is decoded and executed in the same manner as any other instruction.
In a further embodiment a field programmable gate array (FPGA) is used as a coprocessor. Thus, a wide variety of additional instructions can be executed, whereby the instruction variety can be expanded dynamically by means of re-programming the FPGA.